Semiconductor memory device and methods of operating the same

ABSTRACT

A semiconductor memory device comprises a memory cell array including a plurality of memory blocks each including a plurality of pages, wherein each of the plurality of pages includes at least one flag cell indicating whether data is in a corresponding page, and a peripheral circuit configured to read data of flag cells of a selected memory block in response to an erase request and to omit an erase operation on the selected memory block based on the data of the flag cells.

CROSS-REFERENCE TO RELATED APPLICATION

Priority to Korean patent application number 10-2012-0086902 filed onAug. 8, 2012, the entire disclosure of which is incorporated byreference herein, is claimed.

BACKGROUND

Various embodiments of the present invention relate generally to asemiconductor memory device and methods of operating the same.

Semiconductor memory is a memory device comprising of semiconductormaterials, such as silicon (Si), germanium (Ge), gallium arsenide(GaAs), and indium phosphide (InP), and chiefly divided into volatileand nonvolatile types.

Volatile memory is a memory device in which data stored therein is lostwhen the supply of power is blocked. Different types of volatile memoryinclude static RAM (SRAM), dynamic RAM (DRAM), and synchronous DRAM(SDRAM). Nonvolatile memory is a memory device that retains data storedtherein even when the supply of power is blocked. Different types ofnonvolatile memory includes ROM (Read Only Memory), programmable ROM(PROM), electrically programmable ROM (EPROM), electrically erasable andprogrammable ROM (EEPROM), flash memory, phase-change RAM (PRAM),magnetic RAM (MRAM), resistive RAM (RRAM), and ferroelectric RAM(FRAM).Flash memory is chiefly divided into NOR and NAND types.

The memory cell of a semiconductor memory device, such as flash memory,is supplied with high voltage when a program operation and an eraseoperation are performed. The memory cell of the semiconductor memorydevice gradually deteriorates as the program/erase cycle increases, atwhich the threshold voltage of the memory cell rises even though datastored remains unchanged. This lowers the reliability of thesemiconductor memory device.

BRIEF SUMMARY

Various embodiments of this disclosure are directed to reducing thedeterioration of a semiconductor memory device.

A semiconductor memory device in accordance with an embodiment of thepresent invention comprises a memory cell array including a plurality ofmemory blocks each including a plurality of pages, wherein each of theplurality of pages includes at least one flag cell indicating whetherdata is stored in a corresponding page, and a peripheral circuitconfigured to read data from the flag cells of a selected memory blockin response to an erase request and to omit an erase operation on theselected memory block based on the data of the flag cells.

The peripheral circuit may be configured to omit the erase operationwhen the flag cells of the selected memory block are in an erase state.

The peripheral circuit may be configured to perform the erase operationwhen at least one of the flag cells of the selected memory block is in aprogram state.

The peripheral circuit may be configured to program the at least oneflag cell when a program operation before the erase request is receivedis performed on each of the plurality of pages.

The plurality of pages may include a plurality of even and odd pages,and may further include first flag cells indicating whether data isstored in the plurality of even pages and second flag cells indicatingwhether data is stored in the plurality of odd pages.

The peripheral circuit may be configured to read data from the firstflag cells of the selected memory block and data from the second flagcells of the selected memory block and to omit the erase operation basedon the read data.

In another embodiment, a method of erasing a semiconductor memory deviceincludes reading data from flag cells corresponding to a plurality ofpages of a selected memory block in response to an erase request, andomitting an erase operation on the selected memory block based on theread data. Each of the flag cells indicates whether data is stored inthe plurality of pages.

A semiconductor memory device in accordance with another embodiment ofthe present invention comprises a memory cell array including aplurality of memory blocks each including a plurality of pages, whereineach of the plurality of pages includes at least one flag cellindicating whether data is stored in a corresponding page, and aperipheral circuit configured to read data from the flag cells of aselected memory block in response to an erase request, and to perform asoft erase operation on the selected memory block using a first erasepulse that is lower than a second erase pulse of a normal eraseoperation based on the read data.

The peripheral circuit may be configured to perform the soft eraseoperation when the flag cells of the selected memory block are in anerase state.

The peripheral circuit may be configured to perform the normal eraseoperation on the selected memory block when at least one of the flagcells of the selected memory block is in a program state.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing a semiconductor memory device inaccordance with an embodiment of the present invention;

FIG. 2 is a circuit diagram showing one of a plurality of memory blocksshown in FIG. 1;

FIG. 3 is a block diagram conceptually showing a first memory block;

FIG. 4 is a flowchart illustrating a method of programming thesemiconductor memory device in accordance with an embodiment of thisdisclosure;

FIG. 5 is a diagram showing distributions of the threshold voltages ofthe memory cells within the memory cell array shown in FIG. 1;

FIG. 6 is a flowchart illustrating an erase method in accordance with anembodiment of the present invention;

FIG. 7 is a table showing voltages supplied to a selected memory blockwhen reading data from the flag cells of the selected memory block;

FIG. 8 is a flowchart illustrating an erase method in accordance withanother embodiment of the present invention;

FIG. 9 is a circuit diagram showing another embodiment of the memoryblock of FIG. 1;

FIG. 10 is a block diagram conceptually showing the memory block of FIG.9;

FIG. 11 is a flowchart illustrating an erase method in accordance withanother embodiment of the present invention; and

FIG. 12 is a table illustrating step S530 of FIG. 11 in more detail.

DESCRIPTION OF EMBODIMENTS

Hereinafter, various embodiments of the present invention will bedescribed in detail with reference to the accompanying drawings. Thefigures are provided to allow those having ordinary skill in the art tounderstand the scope of the embodiments of the present invention.

Throughout this specification, an element that is “coupled (orconnected)” to the other element may refer to one element “directlycoupled (or connected)” to the other element or “electrically coupled(or connected)” to the other element through a third element.Furthermore, when one part “includes (or comprises)” the other part, theone part may further include other elements unless otherwise specified.

FIG. 1 is a block diagram showing a semiconductor memory device 100 inaccordance with an embodiment of this disclosure, FIG. 2 is a circuitdiagram showing one (for example, BLK1) of a plurality of memory blocksBLK1˜BLKz shown in FIG. 1, and FIG. 3 is a block diagram conceptuallyshowing a first memory block BLK1.

Referring first to FIG. 1, the semiconductor memory device 100 includesa memory cell array 110 and a peripheral circuit 120 configured to drivethe memory cell array 110.

The memory cell array 110 is coupled to an address decoder 121 throughrow lines RL, which include a drain select line, word lines, and asource select line, and is coupled to a read/write circuit 122 throughbit lines BL. Each of a plurality of memory blocks BLK1˜BLKz includes aplurality of memory cells. Memory cells disposed in a row direction arecoupled to the word lines, and memory cells disposed in a columndirection are coupled to the bit lines BL.

Referring to FIG. 2, the first memory block BLK1 is coupled to theread/write circuit 122 through first to m^(th) bit lines BL1˜BLm, and isalso. coupled to the address decoder 121 through the common source lineCSL and row lines RL (refer to FIG. 1)

The first memory block BLK1 includes first to m^(th) cell stringsCS1˜CSm, which are coupled to the first to m^(th) bit lines BL1˜BLm,respectively. Each of the cell strings includes a source selecttransistor SST coupled to the source select line SSL, first to n^(th)memory cells M1˜Mn coupled to the first to n^(th) word lines WL1˜WLn,respectively, and a drain select transistor DST coupled to the drainselect line DSL. The source terminals of the source select transistorsSST of the cell strings are coupled to the common source line CSL, andthe drain terminals of the drain select transistors DST of the cellstrings are coupled to the first to m^(th) bit lines BL1˜BLm.

In accordance with an embodiment of the present invention, the firstmemory block BLK1 is divided into a main region MA and a flag region FA,where the main region MA comprises of the first to (m-1)^(th) cellstrings CS1˜CSm-1, and the flag region FA comprises of a m^(th) cellstring CSm. In FIG. 2, the flag region FA is illustrated as includingone cell string CSm, but this is only illustrative as it may include aplurality of cell strings.

Data, such as an externally received data DATA (refer to FIG. 1) isstored in the memory cells of the main region MA (hereinafter referredto as main memory cells). Data indicating whether data DATA has beenstored in the main memory cells is stored in the memory cells of theflag region FA (hereinafter referred to as flag memory cells).

Each of the second to z^(th) memory blocks BLK2˜BLKz may be configuredlike the first memory block BLK1 described with reference to FIG. 2.

Referring to FIG. 3, memory cells coupled to one word line form onephysical page. Memory cells coupled to the first word line WL1, secondword line WL2, third word line WL3, and nth word line WLn form a firstphysical page P1, a second physical page P2, a third physical page P3,and an nth physical page Pn, respectively.

Each of the physical pages includes main memory cells coupled to oneword line and one or more flag cells indicating whether data has beenstored in the main memory cells. The first physical page P1, secondphysical page P2, third physical page P3, and nth physical page Pnincludes first main memory cells MC1 and a first flag cell FC1, secondmain memory cells MC2 and a second flag cell FC2, third main memorycells MC3 and a third flag cell FC3, and nth main memory cells MCn andan nth flag cell FCn.

Referring back to FIG. 1, the peripheral circuit 120 includes theaddress decoder 121, the read/write circuit 122, and control logic 123.

The address decoder 121 is coupled to the memory cell array 110 throughthe row lines RL. The address decoder 121 is configured to operate underthe control of the control logic 123 and receives addresses ADDR fromthe outside or from an I/O buffer (not shown) of the semiconductormemory device 100.

The address decoder 121 is configured to decode a block address fromamong the received addresses ADDR, thereby selecting one memory block inresponse to the decoded block address.

The address decoder 121 may decode a row address from among the receivedaddresses ADDR, thereby selecting one of the word lines in response tothe decoded row address.

The address decoder 121 may decode a column address from among thereceived addresses ADDR and send the decoded column address Yi to theread/write circuit 122.

In read and program operations, the addresses ADDR may include the blockaddress, the row address, and the column address. The address decoder121 may select one memory block and one word line in response to theaddresses ADDR and provide the decoded column address Yi to theread/write circuit 122.

In an erase operation, the addresses ADDR may include the block address.The address decoder 121 may select one memory block in response to theaddresses ADDR.

The address decoder 121 may include a block decoder, a row decoder, acolumn decoder, and an address buffer.

The read/write circuit 122 is coupled to the memory cell array 110through the bit lines BL, and is configured to operate under the controlof the control logic 123.

In a program operation and a read operation, the read/write circuit 122exchanges the data DATA with the outside or the I/O buffer (not shown)of the semiconductor memory device 100. Particularly, in a programoperation, the read/write circuit 122 receives the data DATA andtransfers the received data DATA to bit lines indicated by a decodedcolumn address Yi, from among the bit lines BL. The transferred dataDATA is programmed into memory cells coupled to a selected word line. Ina read operation, the read/write circuit 122 reads data from memorycells that are coupled to a selected word line through bit linesindicated by a decoded column address Yi, from among the bit lines BL,and outputs the read data DATA. In an erase operation, the bit lines BLmay be floating.

The read/write circuit 130 may include page buffers or page registersand a column selector.

The control logic 123 is coupled to the address decoder 121 and theread/write circuit 122, receives a control signal CTRL from the outsideor the I/O buffer (not shown) of the semiconductor memory device 100,and is configured to control an overall operation of the semiconductormemory device 100 in response to the control signal CTRL.

In accordance with the present embodiment, the control logic 123controls the address decoder 121 and the read/write circuit 122 so thatdata is read from the flag cells of a selected memory block in responseto the control signal CTRL that requests an erase operation. The controllogic 123 may receive the read data through the read/write circuit 122.The control logic 123 may be configured to omit an erase operation onthe selected memory block according to the read data or when all thedata of the flag cells of a selected memory block is in the erase state.If the execution of the erase operation is selectively omitted asdescribed above, memory cell array 110 may deteriorated less. Thus, whenan erase operation is selectively omitted, the operating speed of thesemiconductor memory device 100 and the operating speed of a controlleroutside the semiconductor memory device 100 may improve.

Although not shown in FIG. 1, the semiconductor memory device 100 mayfurther include the I/O buffer (not shown), which may receive thecontrol signal CTRL and the addresses ADDR from the outside and transferthe addresses ADDR and the control signal CTRL to the address decoder121 and the control logic 123, respectively. It may be configured totransfer external data DATA to the read/write circuit 122 and transferthe data DATA of the read/write circuit 122 to the outside.

In the above embodiments, the semiconductor memory device 100 may be aflash memory device.

FIG. 4 is a flowchart illustrating a method of programming thesemiconductor memory device 100 in accordance with an embodiment of thepresent invention.

Referring to FIGS. 1 and 4, a request for a program operation isreceived at step S110. A control signal CTRL indicating the programoperation, an address ADDR, and data DATA to be programmed may beinputted to the peripheral circuit 120.

At step S120, when the program operation is performed on a selectedphysical page, a flag cell included in the selected physical page isalso programmed. In response to the request, the peripheral circuit 120may program the data DATA into main memory cells of a physical pagecorresponding to the address ADDR. The peripheral circuit 120 programsthe data DATA into the flag cell of the physical page corresponding tothe address ADDR.

Accordingly, when each physical page is programmed, the flag cellincluded in the physical page has a program state.

FIG. 5 is a diagram showing distributions of the threshold voltages ofthe memory cells within the memory cell array 110 shown in FIG. 1.

Referring to FIG. 5, if each of the memory cells are defined as a singlelevel cell (SLC), the memory cells may have an erase state E and a firstprogram state P1. When a selected physical page is programmed, each ofthe memory cells included in the selected physical page may beprogrammed to have the erase state E or the first program state P1 inresponse to data DATA to be programmed (refer to FIG. 1). The flag cellof the selected physical page is programmed to have the first programstate P1, and if a plurality of flag cells is included in the selectedphysical page, all the flag cells may be programmed to have the firstprogram state P1.

If each of the memory cells are defined as a multi-level cell (MLC), thememory cells may have an erase state E and second to fourth programstates P2˜P4. When a selected physical page is programmed, each of thememory cells included in the selected physical page may be programmed tohave one of the erase state E and the second to fourth program statesP2˜P4 in response to data DATA to be programmed. The flag cell of theselected physical page may also be programmed to have a thresholdvoltage that corresponds to one of the second to fourth program statesP2˜P4 for example.

It is hereinafter assumed that each of the memory cells of the memorycell array 110 is an SLC, for convenience of description, but it is tobe noted that the present invention is not limited thereto.

FIG. 6 is a flowchart illustrating an erase method in accordance with anembodiment of the present invention, and FIG. 7 is a table showingvoltages supplied to a selected memory block when reading data from theflag cells of the selected memory block.

Referring first to FIGS. 1 and 6, at step S310, the peripheral circuit120 reads data from the flag cells of a selected memory block inresponse to the control signal CTRL indicating an erase operation.

When reading the data, the bit line BLm may be precharged and voltagesof the row lines RL coupled to the selected memory block may be biased.Referring to FIGS. 2 and 7, the common source line CSL may be suppliedwith a reference voltage Vss such as 0 V, the source select line SSL andthe drain select line DSL of the selected memory block may be suppliedwith a selection voltage Vsel such as 4.5 V, and the first to n^(th)word lines WL1˜WLn may be supplied with a word line voltage Vwl. Theword line voltage Vwl may be voltage between the erase state E (refer toFIG. 5) and the program state P1 such as 0 V.

In accordance with the bias conditions, when all the flag cells are inthe erase state E, electric charges precharged in the bit line BLm maybe discharged to the common source line CSL through the cell string CSm.When at least one of the flag cells is in the program state P1, theelectric charges of the bit line BLm may not be discharged. Theread/write circuit 122 senses the voltage of the bit line BLm and storesdata corresponding to the sensed voltage in an internal latch, which inturn may be transferred to the control logic 123. The control logic 123determines whether all the flag cells are in the erase state E or if atleast one of the flag cells is in the program state P1 or not based onthe receive data.

A method of reading the data from the flag cells may be altered invarious ways. The data may be sequentially read from the flag cellscoupled to the first to n^(th) word lines WL1˜WLn.

Referring back to FIGS. 1 and 6, at step S320, either the eraseoperation is performed at step S330 or the erase operation is omittedentirely depending on whether one or more of the flag cells are in theprogram state.

The erase operation is performed by supplying an erase pulse to a bulkregion corresponding to the selected memory block and repeatedlyperforming a verify operation to determine whether the memory cells ofthe selected memory block have respective threshold voltages each lowerthan a specific voltage. If the verify process passes, a soft programoperation may be further performed.

Since the erase operation is performed on each memory block, data storedin both the main memory cells and flag memory cells of the selectedmemory block, is erased.

FIG. 8 is a flowchart illustrating an erase method in accordance withanother embodiment of the present invention.

Referring to FIG. 8, at step S410, a read operation is performed on theflag cells of a selected memory block. Whether at least one of the flagcells is in a program state is determined at step S420. If it isdetermined that at least one of the flag cells has a program state, stepS430 is performed. Otherwise, step S440 is performed.

Step S430 comprises of a normal erase operation, and step S440 comprisesof a soft erase operation. Like the erase operation described withreference to FIG. 6, the normal erase operation is performed bysupplying an erase pulse to a bulk region corresponding to the selectedmemory block, performing a verify operation to determine whether thememory cells of the selected memory block have respective thresholdvoltages each lower than a specific voltage, and repeating the verifyoperation by supplying an increased erase pulse according to a result ofthe verification. The soft erase operation is performed like the normalerase operation except that an erase pulse lower than the erase pulseused in the normal erase operation is used.

The start voltage of the erase pulse that is used in the soft eraseoperation may be lower than the start voltage of the erase pulse that isused in the normal erase operation. Furthermore, an increment of theerase pulse used in the soft erase operation may be smaller than anincrement of the erase pulse used in the normal erase operation.

Supplying a low erase pulse to the bulk region of the selected memoryblock translates to less deterioration of the selected memory block,thereby causing less deterioration of the memory cell array 110.

FIG. 9 is a circuit diagram showing another embodiment of the memoryblock of FIG. 1.

Referring to FIG. 9, a first memory block BLK1′ includes first to X^(th)even cell strings CSe1˜CSeX and first to X^(th) odd cell stringsCSo1˜CSoX. The first to X^(th) even cell strings CSe1˜CSeX are coupledto first to X^(th) even bit lines BLe1˜BLeX, respectively, and the firstto X^(th) odd cell strings CSo1˜CSoX are coupled to first to X^(th) oddbit lines BLo1˜BLoX, respectively.

A Y^(th) (Y is a natural number equal to or smaller than X) even bitline BLeY and a Y^(th) odd bit line BLoY form a pair of bit lines.Although not shown in FIG. 9, the pair of bit lines is coupled to onepage buffer.

The first memory block BLK1′ is divided into a main region MA and a flagregion FA. In accordance with the present invention, the flag region FAincludes the X^(th) even cell string CSeX, indicating whether data hasbeen stored in the even cell strings CSe1˜CSeX-1 of the main region MA,and the X^(th) odd cell string CSoX, indicating whether data has beenstored in the odd cell strings CSo1˜CSoX-1 of the main region MA.

Each of the first to z^(th) memory blocks BLK1˜BLKz of FIG. 1 may beconfigured like the first memory block BLK1′ described with reference toFIG. 8.

FIG. 10 is a block diagram conceptually showing the first memory blockBLK1′ of FIG. 9.

Referring to FIG. 10, one physical page includes an even page, an oddpage, an even flag cell, and an odd flag cell which correspond to oneword line. The even page (for example, EP1) includes main memory cellscoupled to one word line (for example, WL1) in the even cell stringsCSe1˜CSeX-1 of the main region MA, and the odd page (for example, EP1)includes main memory cells coupled to one word line (for example, WL1)in the odd cell strings CSo1˜CSoX-1 of the main region MA. The even flagcell (for example, EFC1) corresponds to the X^(th) even cell string CSeXof the flag region FA, and the odd flag cell (for example, OFC1)corresponds to the X^(th) odd cell string CSoX of the flag region FA.

When the even page (for example, EP1) is programmed, the even flag cell(for example, EFC1) of a corresponding physical page is programmed, andwhen the odd page (for example, OP1) is programmed, the odd flag cell(for example, OFC1) of a corresponding physical page is programmed.

Accordingly, when an even flag cell has the erase state, it means thatdata is not stored in a corresponding even page, and likewise, when anodd flag cell has the erase state, it means that data is not stored in acorresponding odd page.

FIG. 11 is a flowchart illustrating an erase method in accordance withanother embodiment of the present invention.

Referring to FIGS. 1 and 11, at step S510, data is read from the evenflag cells of a selected memory block. A method of reading the data ofthe even flag cells may be performed like the method described withreference to FIG. 7.

At step S520, data is read from the odd flag cells of the selectedmemory block. A method of reading the data of the odd flag cells may beperformed like the method described with reference to FIG. 7.

FIG. 11 illustrates that the read operation is first performed on theeven flag cells and the read operation is then performed on the odd flagcells, but the order of the read operations may be changed.

At step S530, whether at least one of the even flag cells and the oddflag cells has a program state is determined. If it is determined thatat least one of the even flag cells and the odd flag cells has a programstate, an erase operation is performed at step S540. Otherwise, it isdetermined that at least one of the even flag cells and the odd flagcells does not have a program state, in which case an erase operationmay be omitted.

FIG. 12 is a table illustrating criteria for the determination at stepS530 of FIG. 11.

Referring to FIG. 12, if the even flag cells and the odd flag cells arein a program state, or if the even flag cells are in the erase state andthe odd flag cells are in a program state, or if the even flag cells arein a program state and the odd flag cells are in the erase state, theerase operation may be performed. If the even flag cells and the oddflag cells are in the erase state, an erase operation may be omitted.

Consequently, if it is determined that data has not been stored in boththe even cell strings CSe1˜CSeX-1 and the odd cell strings CSo1˜CSoX-1(refer to FIG. 9) of the main region MA based on data stored in the evenflag cells and data stored in the odd flag cells, an erase operation maybe omitted.

In accordance with the present invention, an erase operation is omittedaccording to the flag cells of a selected memory block, or an eraseoperation using a low erase pulse is performed. Accordingly, the memorycell array 110 is deteriorated less.

What is claimed is:
 1. A semiconductor memory device, comprising: amemory cell array including a plurality of memory blocks each comprisinga plurality of pages, wherein each of the plurality of pages comprisesat least one flag cell indicating whether data is stored in acorresponding page; and a peripheral circuit configured to read datafrom the flag cells of a selected memory block in response to an eraserequest and to omit an erase operation on the selected memory blockbased on the data of the flag cells.
 2. The semiconductor memory deviceof claim 1, wherein the peripheral circuit is configured to omit theerase operation when the flag cells of the selected memory block are inan erase state.
 3. The semiconductor memory device of claim 1, whereinthe peripheral circuit is configured to perform the erase operation whenat least one of the flag cells of the selected memory block is in aprogram state.
 4. The semiconductor memory device of claim 1, whereinthe peripheral circuit is configured to supply an identical voltage toword lines coupled to the flag cells of the selected memory block toread the data of the flag cells.
 5. The semiconductor memory device ofclaim 1, wherein the peripheral circuit is configured to program the atleast one flag cell when a program operation before the erase request isreceived is performed on each of the plurality of pages.
 6. Thesemiconductor memory device of claim 1, wherein data of the flag cellsis erased when an erase operation is performed on the selected memoryblock.
 7. The semiconductor memory device of claim 1, wherein: theplurality of pages comprises a plurality of even pages and a pluralityof odd pages, and the plurality of pages further comprises first flagcells indicating whether data is stored in the plurality of even pages,and second flag cells indicating whether data is stored in the pluralityof odd pages.
 8. The semiconductor memory device of claim 7, wherein theperipheral circuit is configured to read data from the first flag cellsof the selected memory block and data from the second flag cells of theselected memory block and to omit the erase operation based on the readdata.
 9. A method of erasing a semiconductor memory device, the methodcomprising: reading data from flag cells corresponding to a plurality ofpages of a selected memory block in response to an erase request; andomitting an erase operation on the selected memory block based on theread data, wherein each of the flag cells indicates whether data isstored in the plurality of pages.
 10. The method of claim 9, wherein theomitting of the erase operation comprises omitting the erase operationwhen the flag cells are in an erase state.
 11. The method of claim 9,further comprising performing the erase operation when at least one ofthe flag cells is in a program state.
 12. The method of claim 9, furthercomprising programming the each of the flag cells when a programoperation is performed on a corresponding page.
 13. A semiconductormemory device, comprising: a memory cell array including a plurality ofmemory blocks each comprising a plurality of pages, wherein each of theplurality of pages comprises at least one flag cell indicating whetherdata is stored in a corresponding page; and a peripheral circuitconfigured to read data from the flag cells of a selected memory blockin response to an erase request and to perform a soft erase operation onthe selected memory block using a first erase pulse lower than a seconderase pulse of a normal erase operation based on the read data.
 14. Thesemiconductor memory device of claim 13, wherein the peripheral circuitis configured to perform the soft erase operation when the flag cells ofthe selected memory block are in an erase state.
 15. The semiconductormemory device of claim 13, wherein the peripheral circuit is configuredto perform the normal erase operation on the selected memory block whenat least one of the flag cells of the selected memory block is in aprogram state.